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Cadence and Virage Logic Collaborate to Deliver Timing and Signal Integrity Views to Enable Low-Power Design
Collaboration Extends Industry Adoption of ECSM and Noise
Library Support to Virage Logic's IPrima Mobile(TM)
Semiconductor IP Platform
SAN JOSE & FREMONT, Calif.—(BUSINESS WIRE)—Feb. 28, 2005—
Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN) and Virage
Logic Corp. (Nasdaq:VIRL) today announced results of a collaboration
to provide library views to better address low-power, multi-voltage
nanometer design needs. Virage Logic has generated and qualified
timing library views that include the Cadence(R) effective current
source model (ECSM) extensions for accurate supply-voltage delay
prediction and noise library views (cdB) for signal-integrity (SI)
analysis.
When used with the Cadence Encounter(TM) digital IC design
platform, these new library views enable design teams to accurately
account for crosstalk, supply-voltage (IR) drop, voltage and frequency
scaling, and multiple voltage-island support required for advanced
nanometer technologies.
In a single, integrated platform, Virage Logic's IPrima Mobile
includes single- and dual-port STAR SRAMs, Area, Speed and Power
(ASAP) Memory(TM) Ultra-Low-Power Memories, ASAP Logic(TM)
Ultra-Low-Power Standard Cell Libraries, and Base I/O Cells. Support
for cdB is included in the ASAP Logic standard cell products, and the
ASAP Memory embedded memory compilers have been enhanced to enable
noise-library creation (cdB). This is essential to accurately isolate
and correct crosstalk-induced failures that may occur at the interface
to each memory block.
"Our customers demand fast timing closure when they take our
synthesizable cores to silicon," said Tom Chanak, CAD manager at MIPS
Technologies. "At high frequencies, SI has become a critical variable
that needs to be built into any hardening flow. Having SI library
views readily available allows us to get the best out of Cadence
Encounter's automatic SI closure flow, enabling our customers to get
to market faster."
"ECSM models provide the accuracy and flexibility needed for our
IPrima Mobile semiconductor intellectual property (IP) platform for
low-power design," said Brani Buric, senior director of product
marketing at Virage Logic. "The accuracy of current source models such
as ECSM influenced us to support this modeling approach to address the
complex features of nanometer designs. In addition, we worked closely
with Cadence to generate and validate the noise models."
"Virage Logic joins the growing list of leading IP providers that
have adopted ECSM, making it the new de facto standard for nanometer
delay modeling," said Jan Willis, senior vice president, Industry
Alliances, at Cadence. "By enabling designers to detect and repair SI
problems earlier in the design process, they now can bring their
designs to market faster, which is critical in today's competitive
marketplace."
For low-power applications that vary the supply voltage for a more
effective tradeoff between performance and power, these new library
views are essential. The ECSM extensions to the timing libraries
enable accurate prediction of performance at different voltage levels,
including accounting for IR drop, while the noise libraries (cdB)
permit accurate analysis of the combined impact of IR drop and
crosstalk on functionality.
These views are especially important for low-power designs that
use multi-threshold cells and multiple power supplies and are
consequently more sensitive to SI-induced failures. The new library
views are also available for nanometer timing and SI signoff with the
Cadence CeltIC(TM) crosstalk analyzer and the SignalStorm(R) NDC
nanometer delay calculator.
About Virage Logic's IPrima Mobile Platform
Created for the portable and hand-held market, the IPrima Mobile
semiconductor IP platform provides several static and dynamic power
saving features all designed to extend the battery life while
maximizing performance by reducing up to 20X static and 80 percent
dynamic power dissipation. IPrima Mobile builds on Virage Logic's
three-plus years of silicon-proven experience in thousands of
high-volume consumer products to provide SoC designers with a single,
integrated IP platform that enables them to efficiently develop
consumer products with longer battery life.
Availability
cdB noise model support is available with recent releases of ASAP
Logic Standard Cell Libraries and ASAP Memory Compilers. ECSM model
support will be available in certain IPrima IP components starting in
the second half of 2005. Contact the local Virage Logic sales office
for view availability. Virage Logic sales office contact information
can be found at www.viragelogic.com.
About Virage Logic
Founded in 1996, Virage Logic Corporation (Nasdaq:VIRL) rapidly
established itself as a technology and market leader in providing
advanced embedded memory intellectual property (IP) for the design of
complex integrated circuits. Today the company is a global leader in
semiconductor IP platforms comprising embedded memories, standard
cells, and I/Os and is pioneering the development of a new class of IP
called Silicon Aware IP. Silicon Aware IP tightly integrates Physical
IP (memory, logic and I/Os) with the embedded test, diagnostic, and
repair capabilities of Infrastructure IP to help ensure
manufacturability and optimized yield at the advanced process nodes.
Virage Logic's highly differentiated product portfolio provides higher
performance, lower power, higher density and optimal yield to
foundries, integrated device manufacturers (IDMs) and fabless
customers who develop products for the consumer, communications and
networking, hand-held and portable, and computer and graphics markets.
The company's comprehensive quality efforts are validated in its
FirstPass-Silicon Characterization Lab, which helps ensure high
quality, reliable IP across a wide range of foundries and process
technologies. Headquartered in Fremont, California, Virage Logic has
R&D, sales and support offices worldwide. For more information, visit
www.viragelogic.com.
About Cadence
Cadence is the world's largest supplier of electronic design
technologies and engineering services. Cadence products and services
are used to accelerate and manage the design of semiconductors,
computer systems, networking equipment, telecommunications equipment,
consumer electronics, and other electronics based products. With
approximately 4,900 employees and 2004 revenues of approximately $1.2
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and trades on both the New York Stock Exchange and Nasdaq
under the symbol CDN. More information is available at
www.cadence.com.
SAFE HARBOR STATEMENT FOR VIRAGE LOGIC UNDER THE PRIVATE
SECURITIES LITIGATION REFORM ACT OF 1995:
Statements made in this news release, other than statements of
historical fact, are forward-looking statements, including, for
example, statements relating to trends, business outlook, products,
and customer relationships. Forward-looking statements are subject to
a number of known and unknown risks and uncertainties, which might
cause actual results to differ materially from those expressed or
implied by such statements. These risks and uncertainties include
Virage Logic's ability to forecast its business, including its
revenue, income and order flow outlook; Virage Logic's ability to
execute on its strategy to become a provider of semiconductor IP
platforms; Virage Logic's ability to continue to develop new products
and maintain and develop new relationships with third-party foundries
and integrated device manufacturers; adoption of Virage Logic's
technologies by semiconductor companies and increases or fluctuations
in the demand for their products; the company's ability to overcome
the challenges associated with establishing licensing relationships
with semiconductor companies; the company's ability to obtain royalty
revenues from customers in addition to license fees, to receive
accurate information necessary for calculating royalty revenues and to
collect royalty revenues from customers; business and economic
conditions generally and in the semiconductor industry in particular;
competition in the market for semiconductor IP platforms; and other
risks including those described in the company's Annual Report on Form
10-K for the period ended September 30, 2004, and in Virage Logic's
other periodic reports filed with the SEC, all of which are available
from Virage Logic's website (www.viragelogic.com) or from the SEC's
website (www.sec.gov), and in news releases and other communications.
Virage Logic disclaims any intention or duty to update any
forward-looking statements made in this news release.
Cadence, Cadence logo and SignalStorm are registered trademarks of
Cadence Design Systems, Inc. Encounter and CeltIC are trademarks of
Cadence Design Systems, Inc. Virage Logic is a registered trademark
and IPrima Mobile, ASAP Logic and ASAP Memory are trademarks of Virage
Logic Corp. All trademarks are the property of their respective
owners.
Contact:
Cadence Design Systems Inc.
Bruce Chan, 408-894-2961
chan@cadence.com
or
Virage Logic Corporation
Sabina Burns, 510-743-8115
Sabina.burns@viragelogic.com
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